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Does three-value output performs to two-value output block possible?

Latest Updated:08/01/2005

Question:

The power-on sequence is the order of suppling -10 V to VSS, 5 V to VCC, +15 V to VDD1, and 0 V to VDD2, and then input of a pattern to BI1. GND, NC, and SUBI become 0 V at power-on (of VSS).
At this time, three-value output is performed to the two-value output block. Is such a thing possible?

Answer:

In the case of this product, the internal comparator becomes floating if VCC is not applied, and as a result normal operation is not performed. Regarding the phenomenon described in the question, there is a problem in the power-on sequence, and the phenomenon is probably caused by unstable output. Use the following power-on and power-off sequences.
• Power-on sequence
1. First, apply VCC.
At this time, input pin (TIx, PGx, BIx, SUBI) voltage ≤ VCC.
Moreover, when Vsb = 2 V, VCC must be applied within the prescribed voltage
(recommended range: 2.0 V to 5.5 V).
2. Next, apply Vsb, VDD1, VDD2a, VDD2b, and Vss
At this time, SUBI must be high level (0.8 VCC or higher).

• Power-off sequence.
1. Cut off Vsb, VDD1, VDD2a, VDD2b, and Vss.
SUBI must be high level (0.8 VCC or higher) until VCC is cut off.
2. Cut off VCC.
Cut off VCC when Vsb has become 2 V or lower.
At this time, input pin (TIx, PGx, BIx, SUBI) voltage ≤ VCC.

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