A division instruction (DIV1 instruction) of the SuperH microcomputer supports neither zero division nor overflow detection. Please check for zero division and overflow division before dividing.
For the division instruction (DIVU instruction and DIVS instruction) supported with SH-2A CPU, the zero division exception will be generated when division by zero is executed.
Please refer to the programming manual in each CPU core for the detailed division sequence.
|SuperH RISC engine Family|