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Is the address error handling CPU when E-DMAC address error occur?

Latest Updated:03/26/2009

Question:

Is address error exception handling(CPU address error or DMA address error) generated when E-DMAC address error is occurred (ADE bit of EtherC/E-DMAC status register(EESR) is set)? 

Answer:

When E-DMAC address error is occurred, address error exception handling is not generated.

When ADE bit is set under the condition that ADEIP bit (Address error interrupt permission) of EtherC/E-DMAC status interrupt permission register (EESIPR) is set to "1", EINT0 interruption is generated. 

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