The inside of the LSI can be reset when using the watchdog timer (WDT) in the watchdog timer mode. In this case, is the reset processing same as the processing when providing the reset input to the RES pin from outside the CPU?
When setting the type of watchdog timer (WDT) to the power on reset mode, the same processing shall be applied except that the FRQCR register of the clock pulse generator (CPG) and the WTCNT register and the WTCSR register of the watchdog timer (WDT) are not initialized. For more information, refer to the section of "Watchdog Timer (WDT)" in the Hardware manuals.
|SH7131, SH7132, SH7136, SH7137|
|SH7083, SH7084, SH7085, SH7086|