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Why clock output didn't go well after shifting to master transmission?

Latest Updated:03/01/2002

Question:

I use the 3-wire serial interface of the uPD780034A switching between the slave reception mode and the master transmission mode, but the clock output immediately after switching to master transmission does not go well.
There is no problem for clock output when continuing to transmit.

The settings I use are as follows.

PM22: Input
CSIM30: Enabled, receive-only mode, clock input
PM21: Output, P21 = 0
PM20: Input

During transmission:
CSIM30: Enabled, transmit/receive mode, clock setting
PM22: Output
SIO30 write


Since the P2n latch specification is 0 in the manual, when the port mode (PM2) and latch (P2n) settings are performed first, a low level is output to SCK30.

Answer:

This is the expected operation.
When serial operation is not enabled with CSIM30, the pin operates as a port.
If the port is output and the output latch is 0, a low level is output to the pin.

In order to avoid this, set the port to output with the output latch set to 1, enable serial operation by setting CSIM30, and then set the output latch to 0.

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