During master transmit/master receive operations, I can only get a IIC bus transfer rate which is half of the rate which I set. What could be causing this?
The pull-up resistance of the board may be so high that the SCL rise time is over the limit for the IIC bus. This would trigger the bit synchronization circuit. Therefore, please revise your pull-up resistance to make SCL rise time, within the MCU's permissible current range, to 1000 ns max for up to 100 kbps, or 300 ns max for up to 400 kbps. In addition, the bit synchronization circuit monitors the SCL pin after it is released from being driven low, to check whether SCL has risen to high level or not. During the monitoring period, IIC is determined by the IICX bit and IIC2 by the CKS3 and CKS2 bits, according to the transfer rate which was set. If the SCL pin cannot be confirmed to be high level during this monitoring, the bit synchronization circuit judges this as SCL having not yet risen to high level, and essentially skips one SCL fall time. As a result, output becomes half (high:low = 3:1) of the transfer rate which was set.
|H8S/2630, 2639, 2638, 2636, 2635|
|H8S/2556, 2552, 2506|
|H8S/2472, 2463, 2462|
|H8S/2258, 2239, 2238, 2237, 2227|