Taken from the term originally used to refer to design in the construction field, in the computer field, architecture means the basic design of a computer system.
In the microcontroller field, the term architecture specially refers to the following.
- Data bit width
- Address space and bank configuration
- Instruction set and addressing mode
- Resource allocation (memories, registers, etc.)
- Pipeline configuration
- Internal bus configuration
- Cache memory configuration
The bank configuration is used to control the address spaces in a multidimensional way.
Addressing is the means by which the address where data is to be read or written is specified. The following types of addressing are commonly used.
Direct addressing : The address is directly specified.
Relative addressing : An address relative to the actual address is specified by specifying a displacement (offset) value.
Indirect addressing : The address is directly/indirectly indicated by a specified register value.
A pipeline is a set of processing stages—such as instruction fetching or data processing—executed in series. A pipeline structure can be used to prevent bottlenecks that hold up instruction execution until the execution of a previous instruction is complete.
In a "superscalar" pipeline configuration, multiple pipelines are used to execute processing in parallel.
In terms of internal bus configuration, a characteristic example can be found in Harvard architecture. In this architecture, the buses used for instruction fetching and transmitting data are separate, eliminating the need for wait cycles to be generated for each processing in the pipeline by bus arbitration.
Cache memory is a memory structure that manages copies of data from the most frequently used address spaces. The cache memory improves system efficiency because it eliminates the need for large address spaces to be constantly accessed. If the processor does not score a hit in the cache area, a replacement operation is executed by which an old cache data item is evicted and the current data item to be accessed is entered into the cache.